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rev. a a ad1838a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. 2 adc, 6 dac, 96 khz, 24-bit - codec features 5 v stereo audio system with 3.3 v tolerant digital interface supports up to 96 khz sample rates 192 khz sample rate available on 1 dac supports 16-, 20-, 24-bit word lengths multibit - modulators with perfect differential linearity restoration for reduced idle tones and noise floor data directed scrambling dacs?east sensitive to jitter differential output for optimum performance adcs: ?5 db thd + n, 105 db snr and dynamic range dacs: ?5 db thd + n, 108 db snr and dynamic range on-chip volume controls per channel with 1024 step linear scale dac and adc software controllable clickless mutes digital de-emphasis processing supports 256 f s , 512 f s , and 768 f s master mode clocks power-down mode plus soft power-down mode flexible serial data port with right-justified, left- justified, i 2 s compatible, and dsp serial port modes tdm interface mode supports 8 in/8 out using a single sharc sport 52-lead mqfp plastic package applications dvd video and audio players home theater systems automotive audio systems audio/visual receivers digital audio effects processors functional block diagram adclp adcln adcrp adcrn dlrclk dbclk dsdata1 dsdata2 dsdata3 dauxdata aauxda ta 3 outlp1 outln1 control port clock filtd filtr mclk asdata abclk alrclk odvdd dvdd av d d av d d dvdd a gnd agnd a gnd a gnd dgnd dgnd cin clatch cclk cout digital filter pd / rst m /s ? ? adc volu me serial data i/o port digital filter - dac v ref outrp1 outrn1 volu me outlp2 outln2 volu me digital filter - dac outrp2 outrn2 volu me outlp3 outln3 volu me digital filter - dac outrp3 outrn3 volu me digital filter ? ? adc ad1838a general description the ad1838a is a high performance single-chip codec featuring three stereo dacs and one stereo adc. each dac comprises a high performance digital interpolation filter, a multibit - modulator featuring analog devices?patented technology, and a continuous-time voltage out analog section. each dac has independent volume control and clickless mute functions. the adc comprises two 24-bit conversion channels with multibit - modulators and decimation filters. the ad1838a also contains an on-chip reference with a nomi- nal value of 2.25 v. the ad1838a contains a flexible serial interface that allows glueless connection to a variety of dsp chips, aes/ebu receivers, and sample rate converters. the ad1838a can be configured in left-justified, right-justified, i 2 s, or dsp com- patible serial modes. control of the ad1838a is achieved by means of an spi compatible serial port. while the ad1838a can be operated from a single 5 v supply, it also features a sepa- rate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 v power supplies. the ad1838a is available in a 52-lead mqfp package and is specified for the industrial temperature range of ?0? to +85?.
rev. a e2e ad1838a test conditions supply voltages (avdd, dvdd) 5.0 v ambient temperature 25 c input clock 12.288 mhz (256 f s mode) dac input signal 1.0078125 khz, 0 dbfs (full scale) adc input signal 1.0078125 khz, e1 dbfs input sample rate (f s ) 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance 100 pf load impedance 47 k performance of all channels is identical (exc ept for the interchannel gain mismatch and interchannel phase deviation speci- fications). parameter min typ max unit analog-to-digital converters adc resolution 24 bits dynamic range (20 hz to 20 khz, e60 db input) no filter 100 103 db with a-weighted filter 105 db total harmonic distortion + noise (thd + n) 48 khz e95 e88.5 db 96 khz e95 e87.5 db interchannel isolation 100 db interchannel gain mismatch 0.025 db analog inputs differential input range ( full scale) e2.828 +2.828 v common-mode input voltage 2.25 v input impedance 4 k input capacitance 15 pf v ref 2.25 v dc accuracy gain error 5% gain drift 35 ppm/?c digital-to-analog converters dac resolution 24 bits dynamic range (20 hz to 20 khz, e60 dbfs input) no filter 103 105 db with a-weighted filter (48 khz and 96 khz) 105 108 db total harmonic distortion + noise (48 khz and 96 khz) e95 e90 db interchannel isolation 110 db dc accuracy gain error 4.0 % interchannel gain mismatch 0.025 db gain drift 200 ppm/ c interchannel phase deviation 0.1 degrees volume control step size (1023 linear steps) 0.098 % volume control range (maximum attenuation) 60 db mute attenuation e100 db de-emphasis gain error 0.1 db full-scale output voltage at each pin (single-ended) 1.0 (2.8) v rms (v p-p) output resistance at each pin 180 common-mode output voltage 2.25 v adc decimation filter, 48 khz * pass band 21.77 khz pass-band ripple 0.01 db stop band 26.23 khz stop-band attenuation 120 db group delay 910 s especifications
rev. a e3e ad1838a parameter min typ max unit adc decimation filter, 96 khz * pass band 43.54 khz pass-band ripple 0.01 db stop band 52.46 khz stop-band attenuation 120 db group delay 460 s dac interpolation filter, 48 khz * pass band 21.77 khz pass-band ripple 0.06 db stop band 28 khz stop-band attenuation 55 db group delay 340 s dac interpolation filter, 96 khz * pass band 43.54 khz pass-band ripple 0.06 db stop band 52 khz stop-band attenuation 55 db group delay 160 s dac interpolation filter, 192 khz * pass band 81 khz pass-band ripple 0.06 db stop band 97 khz stop-band attenuation 80 db group delay 110 s digital i/o input voltage high 2.4 v input voltage low 0.8 v output voltage high odvdd e 0.4 v output voltage low 0.4 v leakage current 10 a power supplies supply voltage (avdd and dvdd) 4.5 5.0 5.5 v supply voltage (odvdd) 3.0 dvdd v supply current i analog 84 95 ma supply current i analog , power-down 55 67 ma supply current i digital 64 74 ma supply current i digital , power-down 1 4.5 ma dissipation operation, both supplies 740 mw operation, analog supply 420 mw operation, digital supply 320 mw power-down, both supplies 280 mw power supply rejection ratio 1 khz, 300 mv p-p signal at analog supply pins e70 db 20 khz, 300 mv p-p signal at analog supply pins e75 db * guaranteed by design. specifications subject to change without notice.
rev. a ad1838a e4e timing specifications parameter min max unit comments master clock and reset t mh mclk high 15 ns t ml mclk low 15 ns t pdr pd rst spprt p p ds dts tr d dt r s ts tr t r t t d td ts tts tr dsrprt ms d d d d d d s ds drs tdr d dr dr dds dsdts tdr dd dsdt dr pms d d d d d d s ds drs tdr d dr dr dds dsdts tdr dd dsdt dr dsrprt mm d d mr d rd dd sdtd ms s s rs tr r r dd sdtd pmm pd d mr pd rd pdd sdtd
rev. a e5e ad1838a parameter min max unit comments tdm256 mode (master, 48 khz and 96 khz) t tbd bclk delay 40 ns from mclk rising edge t fsd fstdm delay 5 ns from bclk rising edge t tabdd asdata delay 10 ns from bclk rising edge t tdds dsdata1 setup 15 ns to bclk falling edge t tddh dsdata1 hold 15 ns from bclk falling edge tdm256 mode (slave, 48 khz and 96 khz) f ab bclk frequency 256 f s t tbch bclk high 17 ns t tbcl bclk low 17 ns t tfs fstdm setup 10 ns to bclk falling edge t tfh fstdm hold 10 ns from bclk falling edge t tbdd asdata delay 15 ns from bclk rising edge t tdds dsdata1 setup 15 ns to bclk falling edge t tddh dsdata1 hold 15 ns from bclk falling edge tdm512 mode (master, 48 khz) t tbd bclk delay 40 ns from mclk rising edge t fsd fstdm delay 5 ns from bclk rising edge t tabdd asdata delay 10 ns from bclk rising edge t tdds dsdata1 setup 15 ns to bclk falling edge t tddh dsdata1 hold 15 ns from bclk falling edge tdm512 mode (slave, 48 khz ) f ab bclk frequency 512 f s t tbch bclk high 17 ns t tbcl bclk low 17 ns t tfs fstdm setup 10 ns to bclk falling edge t tfh fstdm hold 10 ns from bclk falling edge t tbdd asdata delay 15 ns from bclk rising edge t tdds dsdata1 setup 15 ns to bclk falling edge t tddh dsdata1 hold 15 ns from bclk falling edge auxiliary interface (48 khz and 96 khz) t axds aauxdata setup 10 ns to auxbclk rising edge t axdh aauxdata hold 10 ns from auxbclk rising edge t dxd dauxdata delay 20 ns from auxbclk falling edge f abp auxbclk frequency 64 f s slave mode t axbh auxbclk high 15 ns t axbl auxbclk low 15 ns t axls auxlrclk setup 10 ns to auxbclk rising edge t axlh auxlrclk hold 10 ns from auxbclk rising edge master mode t auxbclk auxbclk delay 20 ns from mclk rising edge t auxlrclk auxlrclk delay 15 ns from auxbclk falling edge specifications subject to change without notice. mclk t mh p d / rst t ml t pdr t mclk figure 1. mclk and pd rst t
rev. a ad1838a e6e ordering guide model temperature range package description package option ad1838aas e40 c to +85 c 52-lead mqfp s-52-1 ad1838aas-reel e40 c to +85 c 52-lead mqfp s-52-1 ad1838aasz * e40 c to +85 c 52-lead mqfp s-52-1 AD1838AASZ-REEL * e40 c to +85 c 52-lead mqfp s-52-1 eval-ad1838aeb e40 c to +85 c 52-lead mqfp s-52-1 * z = pb-free part. temperature range parameter min typ max unit specifications guaranteed 25 c functionality guaranteed e40 +85 c storage e65 +150 c absolute maximum ratings * (t a = 25 c, unless otherwise noted.) avdd, dvdd, odvdd to agnd, dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +6 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v digital i/o voltage to dgnd . . . e0.3 v to odvdd + 0.3 v analog i/o voltage to agnd . . . . . e0.3 v to avdd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . e40 c to +85 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1838a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a ad1838a e7e pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 agnd avdd outrp2 outrn2 outlp2 outln2 outrp1 outrn1 outlp1 outln1 pd / rst cin clatch dvdd outln3 outlp3 dgnd 52 51 50 49 48 47 46 45 44 43 42 41 40 filtd filtr agnd dauxdata agnd avdd adcln adclp adcrn adcrp agnd dgnd cclk cout asdata odvdd mclk alrclk abclk aauxdata3 dsdata3 dsdata2 dsdata1 ad1838a top view (not to scale ) outrn3 outrp3 n/c n/c n/c agnd agnd dlrclk dbclk 27 28 29 30 31 32 33 34 35 36 37 38 39 m /s dvdd avdd 14 15 16 17 18 19 20 21 22 23 24 25 26 pin function descriptions input/ pin no. mnemonic output description 1, 39 dvdd digital power supply. connect to digital 5 v supply. 2c latch i latch input for control data. 3 cin i serial control input. 4 pd rst pdr d t d tp dp tr dr trp drp dd ps td r tr r r d d dp dp dr dr drp drp m s dmss ddt dd dr dr d d dd d dsdt ddr dt dd d r dr m m ddd ddps sdt dsd t d d
rev. a ad1838aetypical performance characteristics e8e frequency e normalized to f s 05 magnitude e db 10 e 150 15 e 100 e50 0 tpc 1. adc composite filter response frequency e hz e30 020 5 magnitude e db 10 15 e25 e20 e15 e10 e5 0 5 tpc 2. adc high-pass filter response, f s = 48 khz frequency e normalized to f s e 150 0 2.0 0.5 magnitude e db 1.0 1.5 0 e 100 e50 tpc 3. adc composite filter response (pass-band section) frequency e hz e30 020 5 magnitude e db 10 15 e25 e20 e15 e10 e5 0 5 tpc 4. adc high-pass filter response, f s = 96 khz frequency e khz 0 e50 e150 magnitude e db e100 0 200 50 100 150 tpc 5. dac composite filter response, f s = 48 khz 0 e50 e 150 e 100 0 200 50 100 150 frequency e khz magnitude e db tpc 6. dac composite filter response, f s = 96 khz
rev. a ad1838a e9e 0 e50 0 200 50 100 150 e100 e 150 frequency e khz magnitude e db tpc 7. dac composite filter response, f s = 192 khz 0.10 0.05 e0.10 020 51015 0 e 0.05 frequency e khz magnitude e db tpc 8. dac composite filter response, f s = 48 khz (pass-band section) 0.2 0.1 e 0.2 050 10 20 30 40 0 e 0.1 frequency e khz magnitude e db tpc 9. dac composite filter response, f s = 96 khz (pass-band section) 0.10 0.05 e0.10 0 100 20 40 60 80 0 e 0.05 frequency e khz magnitude e db tpc 10. dac composite filter response, f s = 192 khz (pass-band section)
rev. a ad1838a e10e terminology dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels. dy namic range is measured with a e60 db input signal and is equal to (s/[thd + n]) + 60 db. note that spurious harmonics are below the noise with a e60 db input, so the noise level es tablishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal-to-(total harmonic distortion + noise) [s/(thd + n)] the ratio of the root-mean-square (rms) value of the fundamen- tal input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. pass band the region of the frequency spectrum unaffected by the attenu- ation of the digital decimator?s filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimator?s filter to the degree specified by stop-band attenuation. gain error with identical near full-scale inputs, the ratio of actual output to expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. crosstalk (eiaj method) ratio of response on one channel with a grounded input to a full-scale 1 khz sine wave input on the other channel, ex pressed in decibels. power supply rejection with no analog input, signal present at the output when a 3 00 mv p-p signal is applied to the power supply pins, ex pressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converter?s output, expressed in microseconds. more precisely, the derivative of radian phase with respect to the radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds. acronyms adc?analog-to-digital converter. dac?digital-to-analog converter. dsp?digital signal processor. imclk?internal master clock signal used to clock the adc and dac engines. mclk?external master clock signal applied to the ad1838a.
rev. a ad1838a e11e table i. coding scheme code level 0111 . . . . 11111 +fs 0000 . . . . 00000 0 (ref level) 1000 . . . . 00000 efs ad1838a clocking scheme by default, the ad1838a requires an mclk signal that is 256 times the required sample frequency up to a maximum of 12.288 mhz. the ad1838a uses a clock scaler to double the clock frequency for use internally. the default setting of the clock scaler is multiply by 2. the clock scaler can also be set multiply by 1 (bypass) or by 2/3. the clock scaler is controlled by programming the bits in the adc control 3 register. the internal mclk signal, imclk, should not exceed 24.576 mhz to ensure correct operation. the mclk of the ad1838a should remain constant during normal operation of the dac and adc. if it is required to change the mclk rate, then the ad1838a should be reset. additionally, if mclk scaler needs to be modified so that the imclk does not exceed 24.576 mhz, this should be done during the internal reset phase of the ad1838a by programming the bits in the first 3072 mclk periods following the reset. selecting dac sampling rate the ad1838a dac engine has a programmable interpolator that allows the user to select different interpolation rates based on the required sample rate and mclk value available. table ii shows the settings required for sample rates based on a fixed mclk of 12.288 mhz. table ii. dac sample rate settings sample rate interpolator rate dac control 1 register 48 khz 8 000000xxxxxxxx00 96 khz 4 000000xxxxxxxx01 192 khz 2 000000xxxxxxxx10 selecting an adc sample rate the ad1838a adc engine has a programmable decimator that allows the user to select the sample rate based on the mclk value. by default, the output sample rate is imclk/512. to achieve a sample rate of imclk/256, the sample rate bit in the adc control 1 register should be set as shown in table iii. table iii. adc sample rate settings sample rate adc control 1 register imclk/512 1100000xx0xxxxxx (48 khz) imclk/256 1100000xx1xxxxxx (96 khz) to maintain the highest performance possible, it is recommended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to-edge technique. even at these levels, extra noise or tones may appear in the dac outputs if the jitter spectrum contains large spectral peaks. it is highly recom- mended that the master clock be generated by an independent crystal oscillator. in addition, it is especially important that the clock signal should not be passed through an fpga or other large digital chip before being applied to the ad1838a. in most cases, this will induce clock jitter because the clock signal is sharing common power and ground connections with other unrelated digital output signals. functional overview adcs there are two adc channels in the ad1838a, configured as a stereo pair. each adc has fully differential inputs. the adc section can operate at a sample rate of up to 96 khz. the adcs include on-board digital decimation filters with 120 db stop- band attenuation and linear phase response, operating at an oversam- pling ratio of 128 (for 48 khz operation) or 64 (for 96 khz operation). adc peak level information for each adc may be read from the adc peak 0 and adc peak 1 registers. the data is sup plied as a 6-bit word with a maximum range of 0 db to e63 db and a resolution of 1 db. the registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. refer to the register description for details of the format. the two adc channels have a common serial bit clock and a left-right framing clock. the clock sig nals are all synchronous with the sample rate. the adc digital pins, abclk and alrclk, can be set to operate as inputs or outputs by connecting the m s dddddw d w d td d d drd tdm dd dtdd d t d r ttd t dd dd tdd t tt
rev. a ad1838a e12e reset and power-down pd / rst powers down the chip and sets the control registers to their default settings. after pd / rst is de-asserted, an initializa- tion routine runs inside the ad1838a to clear all memories to zero. this initialization lasts for approximately 20 lrclk intervals. during this time, it is recommended that no spi writes occur. power supply and voltage reference the ad1838a is designed for 5 v supplies. separate power supply pins are provided for the analog and digital sections. these pins should be bypassed with 100 nf ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pc board as the codec. for critical appli- cations, improved performance will be obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital supplies be isolated by two ferrite beads in series with the bypass capacitor of each supply. it is important that the analog supply be as clean as possible. t he internal voltage reference is brought out on the filtr pin and should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. the reference volt- age may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. the current drawn from the filtr pin should be limited to less than 50 a. serial control port the ad1838a has an spi compatible control port to permit programming the internal control registers for the adcs and dacs and to read the adc signal levels from the internal peak detectors. the spi control port is a 4-wire serial control port. the format is similar to the motorola spi format except the input data-w ord is 16 bits wide. the maximum serial bit clock frequency is 12.5 mhz and may be completely asynchronous to the sample rate of the adcs and dacs. figure 3 shows the format of the spi signal. serial data ports?ata format the adc serial data output mode defaults to the popular i 2 s format, where the data is delayed by one bclk interval from the edge of the lrclk. by changing bits 6 to 8 in adc con- trol register 2, the serial mode can be changed to right-justified (rj), left-justified dsp (dsp), or left-justified (lj). in the rj mode, it is necessary to set bits 4 and 5 to define the width of the data-word. dac engine cl ock scaling 1 2 2/3 mclk dac input in terpolation fi lter - modulator dac 48khz/96khz/192khz adc engine adc output o ptional hpf deci mator/ fi lter 48khz/96khz a nalog ou tput a nalog input 12.288mhz imclk = 24.576mhz - modulator figure 2. modulator clocking scheme clatch cclk cin cout d0 d8 d0 d15 d14 d9 d8 t cch t ccl d9 t cds t cdh t cls t clh t cod t cots t ccp t coe figure 3. format of spi timing
rev. a ad1838a e13e the dac serial data input mode defaults to i 2 s. by changing bits 5, 6, and 7 in dac control register 1, the mode can be changed to rj, dsp, lj, or packed mode 256. the word width defaults to 24 bits but can be changed by re programming bits 3 and 4 in dac control register 1. packed modes the ad1838a has a packed mode that allows a dsp or other controller to write to all dacs and read all adcs using one input data pin and one output data pin. packed mode 256 refers to the number of bclks in each frame. the lrclk is low while data from a left channel dac or adc is on the data pin, and high while data from a right channel dac or adc is on the data pin. dac data is applied on the dsdata1 pin, and adc data is available on the asdata pin. figures 7 to 10 show the timing for the packed mode. packed mode is available for 48 khz and 96 khz. auxiliary (tdm) mode a special auxiliary mode is provided to allow three external stereo adcs and one external stereo dac to be interfaced to the ad1838a to provide 8-in/8-out operation. in addition, this mode supports glueless interface to a single sharc dsp serial port, allowing a sharc dsp to access all eight channels of analog i/o. in this special mode, many pins are redefined; see table iv for a list of rede fined pins. the auxiliary and the tdm interfaces are independently configurable to operate as masters or slaves. when the auxiliary interface is set as a master, by programming the a uxiliary mode bit in adc con trol register 2, the auxlrclk and auxbclk are generated by the ad1838a. when the auxiliary interface is set as a slave, the auxlrclk and auxbclk need to be generated by an exter- nal adc, as shown in figure 13. the tdm interface can be set to operate as a master or slave by connecting the m s ddddd stdm d s tdm sr mmm r sdt r sdt r sdt r sdt t rt t rt t rt ms ms ms ms ms ms ms ms s s s s s s s s tstdmdtsttspr s mdtsttspr rtstdmdstmrtspr dspmdtsttspr s ts dspmddstdt rrmprtst s ptrdspmdws s rsrm rtmprtdrstmd ssm
rev. a ad1838a e14e t als abclk alrclk asdata le ft-justified mode asdata r ight-justified mode lsb asdata i 2 s compatible mode t abh t abl msb msb-1 msb msb t alh t abdd figure 5. adc serial mode timing t dls dbclk dlrclk dsdata le ft-justified mode dsdata r ight-justified mode lsb dsdata i 2 s compatible mode t dbh t dbl t dds msb msb-1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb t dlh figure 6. dac serial mode timing
rev. a ad1838a e15e lrclk bclk adc data slot 1 left slot 2 slot 5 right slot 6 msb msb e 1 msb e 2 16 bclks 128 bclks slot 3 slot 4 slot 7 slot 8 figure 7a. adc packed mode 128 lrclk bclk adc data slot 1 left slot 2 slot 5 right slot 6 msb msb e 1 msb e 2 32 bclks 256 bclks slot 3 slot 4 slot 7 slot 8 figure 7b. adc packed mode 256 lrclk bclk dac data slot 1 left 1 slot 5 right 1 msb msb e 1 msb e 2 16 bclks 128 bclks slot 2 left 2 slot 3 left 3 slot 4 left 4 slot 6 right 2 slot 7 right 3 slot 8 right 4 figure 8a. dac packed mode 128 lrclk bclk dac data slot 1 left 1 slot 5 right 1 msb msb e 1 msb e 2 32 bclks 256 bclks slot 2 left 2 slot 3 left 3 slot 4 left 4 slot 6 right 2 slot 7 right 3 slot 8 right 4 figure 8b. dac packed mode 256
rev. a ad1838a e16e t als abclk alrclk asdata t abh t abl msb msb e 1 t alh t abdd figure 9. adc packed mode timing t dls dbclk dlrclk dsdata t dbh t dbl t dds msb msb e 1 t ddh t dlh figure 10. dac packed mode timing
rev. a ad1838a e17e table iv. pin function changes in auxiliary mode pin name i 2 s mode auxiliary mode asdata (o) i 2 s data out, internal adc tdm data out to sharc. dsdata1 (i) i 2 s data in, internal dac1 tdm data in from sharc. dsdata2 (i)/aauxdata1 (i) i 2 s data in, internal dac2 aux-i 2 s data in 1 (from external adc). dsdata3 (i)/aauxdata2 (i) i 2 s data in, internal dac3 aux-i 2 s data in 2 (from external adc). aauxdata3 (i) not connected aux-i 2 s data in 3 (from external adc). alrclk (o) lrclk for adc tdm frame sync out to sharc (fstdm). abclk (o) bclk for adc tdm bclk out to sharc. dlrclk (i)/auxlrclk (i/o) lrclk in/out internal dacs aux lrclk in/out. driven by external lrclk from adc in slave mode. in master mode, driven by mclk/512. dbclk (i)/auxbclk (i/o) bclk in/out internal dacs aux bclk in/out. driven by external bclk from adc in slave mode. in master mode, driven by mclk/8. dauxdata (o) not connected aux-i 2 s data out (to external dac). fstdm internal adc l1 aux_adc l2 aux_adc l3 aux_adc l4 internal adc r1 aux_adc r2 aux_adc r3 aux_adc r4 internal dac l1 internal dac l2 internal dac l3 internal dac r1 internal dac r2 internal dac r3 msb tdm 1st ch left right i 2 s e msb right i 2 s e msb left bclk tdm asdata1 tdm (out) asdata dsdata1 tdm (in) dsdata1 aux lrclk i 2 s (from aux adc no. 1) aux bclk i 2 s (from aux adc no. 1) aauxdata1 (in) (from aux adc no. 1) aauxdata2 (in) (from aux adc no. 2) aauxdata3 (in) (from aux adc no. 3) auxbclk frequency is 64 frame rate; tdm bclk frequency is 256 frame rate. tdm interface aux e i 2 s in terface msb tdm 8th ch 32 32 msb tdm 1st ch msb tdm 8th ch i 2 s e msb right i 2 s e msb left i 2 s e msb right i 2 s e msb left internal dac l4 internal dac r4 figure 11. auxiliary mode timing
rev. a ad1838a e18e 30mhz 12.288mhz sharc is always running in slave mode (interrupt driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc no. 2 slave sharc ad1838a master mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc no. 3 slave lrclk bclk data mclk adc no. 1 slave aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac no. 1 slave dauxdata figure 12. auxiliary mode connection (master mode) to sharc 30mhz 12.288mhz sharc is always running in slave mode (interrupt driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc no. 2 slave sharc ad1838a slave mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc no. 3 slave lrclk bclk data mclk adc no. 1 master aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac no. 1 slave dauxdata figure 13. auxiliary mode connection (slave mode) to sharc
rev. a ad1838a e19e control/status registers the ad1838a has 13 control registers, 11 of which are used to set the operating mode of the part. the other two registers, adc peak 0 and adc peak 1, are read-only and should not be programmed. each of the registers is 10 bits wide with the exception of the adc pe ak reading registers, which are 6 bits wide. writing to a con- trol register requires a 16-bit data frame to be transmitted. bits 15 to 12 are the address bits of the required register. bit 11 is a read/write bit. bit 10 is reserved and should always be programmed to 0. bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. figure 3 shows the format of the spi read and write operation. dac control registers the ad1838a register map has eight registers that are used to control the functionality of the dac section of the part. the function of the bits in these registers is discussed below. sample rate these bits control the sample rate of the dacs. based on a 24.576 mhz imclk, sample rates of 48 khz, 96 khz, and 192 khz are available. the mclk scaling bits in adc con- trol register 3 should be programmed appropriately, based on the master clock frequency. power-down/reset this bit controls the power-down status of the dac section. by default, normal mode is selected. but by setting this bit, the digital section of the dac stage can be put into a low power mode, thus reducing the digital current. the analog output section of the dac stage is not powered down. dac data-word width these two bits set the word width of the dac data. compact disk (cd) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. dac data format the ad1838a serial data interface can be configured to be co m patible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. details of these interface modes are given in the serial data port section. de-emphasis the ad1838a provides built-in de-emphasis filtering for the three standard sample rates of 32.0 khz, 44.1 khz, and 48 khz. mute dac each of the six dacs in the ad1838a has its own independent mute control. setting the appropriate bit mutes the dac output. the ad1838a uses a clickless mute function that attenu- ates the output to approximately e100 db over a number of cycles. stereo replicate setting this bit copies the digital data sent to the stereo pair dac1 to the three other stereo dacs in the system. this allows all three stereo dacs to be driven by one digital data stream. note that in this mode, dac data sent to the other dacs is ignored. dac volume control each dac in the ad1838a has its own independent volume control. the volume of each dac can be adjusted in 1024 linear steps by programming the appropriate register. the de fault value for this register is 1023, which provides no attenu- ation, i.e., full volume. adc control registers the ad1838a register map has five registers that are used to control the functionality and to read the status of the adcs. the function of the bits in each of these registers is discussed below. adc peak level these two registers store the peak adc result from each channel when the adc peak readback function is enabled. the peak result is stored as a 6-bit number from 0 db to e63 db in 1 db steps. the value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. note that the adc peak level reg isters use the 6 msb in the register to store the results. sample rate this bit controls the sample rate of the adcs. based on a 24.576 mhz imclk, sample rates of 48 khz and 96 khz are available. the mclk scaling bits in adc control register 3 should be programmed appropriately based on the master clock frequency. adc power-down this bit controls the power-down status of the adc section and operates in a similar manner to the dac power-down. high-pass filter the adc signal path has a digital high-pass filter. enabling this filter removes the effect of any dc offset in the analog input signal from the digital output codes. adc data-word width these two bits set the word width of the adc data. adc data format the ad1838a serial data interface can be configured to be co mpatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. master/slave auxiliary mode when the ad1838a is operating in the auxiliary mode, the auxil- iary adc control pins, auxbclk and auxlrclk, which con nect to the external adcs, can be set to operate as a master or slave. if the pins are set in slave mode, one of the external adcs should provide the lrclk and bclk signals. adc peak readback setting this bit enables adc peak reading. see the adcs section for more information.
rev. a ad1838a e20e table vii. dac control 2 function mute dac stereo address r/ w w w w w w w dtr d r w d d r w d dr r w d d r w d dr r w d d r w d dr r w r r r w r r r r w r dp dp r dp drp r dtr d r w dtr d r w dtr d r w r r r w r t d dd dd pd r w ww
rev. a ad1838a e21e table xii. adc control 3 function r/ w w w w w ww
rev. a ad1838a e22e cascade mode dual ad1838a cascade the ad1838a can be cascaded to an additional ad1838a, which, in addition to six external stereo adcs and one external stereo dac, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. the cascade is designed to connect to a sharc dsp and operates in a time division multiplexing ( tdm) format. figure 14 shows the connection diagram for cascade operation. the digital interface for both parts must be set to operate in auxiliary 512 mode by program- m ing adc control register 2. ad 1838a no. 1 is set as a master device by connecting the m sddd m sddd m pd rst wd tsr d t d td sr dwsr d d srd d d s r sdt dsdt r sdt dsdt d mstr d s sr s dt r d s dt r d s dt r d s dt r d s dt r d s dt r r dt dt dt r dt dt dt dr rs r t dt d s d r ddt d s d r ddt dd dd r r r dd r r r rs dt dd r r r r dd r r r r dr ms ms s dt ms ms s dr d tr r r ddt
rev. a ad1838a e23e 5.76k 100pf npo a udio input 600z + 47 f 5.76k 120pf npo v ref 5.76k 5.76k v ref 750k 237 1nf npo 237 1nf npo 100pf npo adcxp adcxn op275 op275 figure 16. typical adc input filter circuit 3.01k 11k 270pf npo 560pf npo 68pf npo 11k 150pf npo 1.5k 5.62k 5.62k 604 2.2nf npo outnx outpx a udio output op275 figure 17. typical dac output filter circuit
rev. a e24e c03626e0e2/04(a) ad1838a outline dimensions 52-lead metric quad flat package [mqfp] (s-52-1) dimensions shown in millimeters seating plane view a 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 13.45 13.20 sq 12.95 7.80 ref 10.20 10.00 sq 9.80 0.40 0.22 7 0 2.20 2.00 1.80 0.13 min coplanarity 0.25 max 10 6 2 0.23 0.11 compliant to jedec standards ms-022-ac. revision history location page 2/04?data sheet changed from rev. 0 to rev. a. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 deleted clock signals section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added ad1835a clocking scheme section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added table ii and table iii and renumbered following tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to auxiliary (tdm mode) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 changes to figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 changes to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 added figures 7a and 8a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 renamed figure 7 and figure 8 to figure 7b and figure 8b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 changes to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 changes to table viii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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